This invention is directed to module interconnections in system on a chip (SOC) integrated circuits. The advent of increased density integrated circuit manufacture has enabled all or all crucial parts of an end user system to be constructed on a signal integrated circuit. Such integrated circuits are called system on a chip (SOC).
Typically as SOC is constructed using as assortment of previously designed subassemblies. A typical SOC design begins with a system definition. This determines the desired functionality of the SOC. The SOC designer then selects a set of already designed modules to form the desired system. This set of modules may include modules previously designed by the SOC designer or available to the SOC manufacture or modules designed by outside parties available for license to use in the SOC. In some instances a needed module is newly designed or acquired. Part of the selection process includes selecting the set of modules having an aggregate construction size within the budget of the SOC. Integrated circuits are manufactured in slices of silicon of predetermined size. The manufacturing cost of a slice is relatively constant regardless of the number of integrated circuit dies included. Thus more and smaller integrated circuit dies having less electrical circuitry can be fitted on a slice than larger integrated circuit dies. Accordingly, the manufacturing cost of integrated circuits is directly related to its die size. This is in turn related to its electrical complexity. The SOC designer often trades functionality based on electrical complexity with aggregate module size and the consequent cost of manufacture.
The SOC designer then assembles these modules on a single integrated circuit to be manufactured. This process includes forming connections between the modules. These connections often include busses of plural lines in parallel for data and addresses. Determination of the connections between modules in a SOC is often nontrivial. The size of such connections often adversely increases the SOC die size. This typically increases the cost of the SOC. There are often timing issues between modules that must be dealt with in the connections. Busses often involve adverse cross talk between connections or between busses.